The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. As the dimensions of transistors decrease, the thickness of the gate dielectric layer must be reduced to maintain performance with the decreased gate length. However, in order to reduce gate leakage, high dielectric constant (high-k) gate dielectric layers are used which allow lesser physical thicknesses while maintaining the same effective thickness, such as would be provided by a gate dielectric layer used in future technology nodes. The gate dielectric layer further comprises an interfacial layer to reduce damage between the high-k gate dielectric layer and a silicon substrate.
However, there are challenges to implement such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. For example, it is difficult to satisfy a threshold voltage requirement for a semiconductor device if the interfacial layer forms a low-quality interface with a high-density of defects. As the gate length and spacing between devices decrease, these problems are exacerbated.